Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
Functional Description
8.4.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator
to adjust the internal clock (ICLK) clock period. The DLF generates the
DCO divider control bits (DDIV[3:0]) and the DCO stage control bits
(DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the
DDIV and DSTG registers (DDIV[3:0]:DSTG[7:0]) and then adds or
subtracts a value dependent on the relative error in the low-frequency
base clock’s period, as shown in Table 8-1. In some extreme error
conditions, such as operating at a V level which is out of specification,
DD
the DLF may attempt to use a value above the maximum ($9FF) or
below the minimum ($000). In both cases, the value for DDIV will be
between $A and $F. In this range, the DDIV value will be interpreted the
same as $9 (the slowest condition). Recovering from this condition
requires subtracting (increasing frequency) in the normal fashion until
the value is again below $9FF (if the desired value is $9xx, the value may
settle at $Axx through $Fxx, an acceptable operating condition). If the
error is less than ±5 percent, the internal clock generator’s filter stable
indicator (FICGS) is set, indicating relative frequency accuracy to the
clock monitor.
Table 8-1. Correction Sizes from DLF to DCO
Frequency Error
DDVI[3:0]:DSTG[7:0]
Correction
Current to New
DDIV[3:0]:DSTG[7:0]
Relative Correction
in DCO
of IBASE Compared
to f
NOM
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
$xFF to $xDF
$x20 to $x00
$xFF to $xF7
$x08 to $x00
$xFF to $xFE
$x01 to $x00
–2/31
–2/19
–6.45%
IBASE < 0.85 f
–32 (–$020)
–8 (–$008)
–1 (–$001)
+1 (+$001)
+8 (+$008)
+32 (+$020)
NOM
–10.5%
–1.61%
–2.86%
–0.202%
–0.366%
+0.202%
+0.368%
+1.64%
+2.94%
+6.90%
+11.8%
–0.5/31
0.85 f
< IBASE
NOM
IBASE < 0.95 f
–0.5/17.5
–0.0625/31
–0.0625/17.0625
NOM
0.95 f
< IBASE
NOM
IBASE < f
NOM
$xFE to $xFF +0.0625/30.9375
f
< IBASE
NOM
IBASE < 1.05 f
$x00 to $x01
$xF7 to $xFF
$x00 to $x08
$xDF to $xFF
$x00 to $x20
+0.0625/17
+0.5/30.5
+0.5/17
+2/29
NOM
1.05 f
< IBASE
NOM
IBASE < 1.15 f
NOM
1.15 f
< IBASE
NOM
+2/17
x: Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
carries or borrows.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
113
Internal Clock Generator Module (ICG)
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