Freescale Semiconductor, Inc.
Break Module (BRK)
Functional Description
Addr.
Register Name
Bit 7
Bit 15
0
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
1
Bit 0
Bit 8
0
Read:
Break Address Register
14
$FE0C
High (BRKH) Write:
See page 106.
Reset:
0
Read:
Break Address Register
Bit 7
0
6
5
4
3
2
Bit 0
$FE0D
$FE0E
Low (BRKL) Write:
See page 106.
Reset:
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
Register (BSCR) Write:
See page 105.
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 7-2. I/O Register Summary
7.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status
bits can be cleared during the break state. The BCFE bit in the SIM break
flag control register (BFCR) enables software to clear status bits during
the break state. (See 6.8.3 SIM Break Flag Control Register and the
Break Interrupts subsection for each module.)
7.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Break Module (BRK)
103
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