August 27, 1998
GENERAL RELEASE SPECIFICATION
Table 17-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
5C
6C ff
7C
5
3
3
6
5
Increment Byte
— —
↕
↕ —
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR BC dd
EXT CC hh ll
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
— — — — —
— — — — —
IX2
IX1
IX
DC ee ff
EC ff
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR BD dd
EXT CD hh ll
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
IX2
IX1
IX
DD ee ff
ED ff
FD
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM A6 ii
DIR B6 dd
EXT C6 hh ll
2
3
4
5
4
3
Load Accumulator
with Memory Byte
A ← (M)
X ← (M)
— —
↕
↕ —
IX2
IX1
IX
D6 ee ff
E6 ff
F6
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM AE ii
DIR BE dd
EXT CE hh ll
2
3
4
5
4
3
Load Index Register
with Memory Byte
— —
— —
↕
↕
↕ —
IX2
IX1
IX
DE ee ff
EE ff
FE
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
68 ff
78
5
3
3
6
5
Logical Shift Left
(Same as ASL)
C
0
↕
↕
b7
b0
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34 dd
44
54
64 ff
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0
↕
↕
b7
b0
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
11
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30 ii
40
50
60 ff
70
5
3
3
6
5
Negate Byte
(Two’s Complement)
— —
↕
↕
↕
NOP
No Operation
— — — — — INH
9D
2
MC68HC05SB7
REV 2.1
INSTRUCTION SET
MOTOROLA
17-11
FREESCALE [ Freescale ]
