GENERAL RELEASE SPECIFICATION
August 27, 1998
16.1 PEPROM REGISTERS
Two I/O registers control programming and reading of the PEPROM:
•
•
The PEPROM bit select register (PEBSR).
The PEPROM status and control register (PESCR).
16.1.1 PEPROM Bit Select Register (PEBSR)
The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM
array. Reset clears all the bits in the PEPROM bit select register.
BIT 7
PEB7
0
BIT 6
PEB6
0
BIT 5
PEB5
0
BIT 4
PEB4
0
BIT 3
PEB3
0
BIT 2
PEB2
0
BIT 1
PEB1
0
BIT 0
PEB0
0
PEBSR
$000E
R
W
reset:
Figure 16-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not connected to the PEPROM array
These read/write bits are available as storage locations. Reset clears PEB7
and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown in
Table 16-1. Bits PEB2–0 select the PEPROM row, and bits PEB5–3 select the
PEPROM column. Reset clears PEB5–PEB0, selecting the PEPROM bit in row
zero, column zero.
16.1.2 PEPROM Status and Control Register (PESCR)
The PEPROM status and control register (PESCR) controls the PEPROM pro-
gramming voltage. This register also transfers the PEPROM bits to the internal
data bus and contains a flag bit when row zero is selected.
BIT 7
PEDATA
U
BIT 6
0
BIT 5
PEPGM
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
PEPRZF
1
PESCR
$000F
R
W
reset:
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 16-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data
This read-only bit is the state of the PEPROM sense amplifier and shows the
state of the currently selected bit. Reset does not affect the PEDATA bit.
1 = PEPROM data is a logic one.
0 = PEPROM data is a logic zero.
MOTOROLA
16-2
PERSONALITY EPROM
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
