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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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GENERAL RELEASE SPECIFICATION  
August 27, 1998  
Table 15-8. Voltage Comparator Setup Conditions  
Current  
Source  
Enable  
Discharge  
Device  
Disable  
Prog. Timer  
Input Capture  
Source  
Port B Pin  
as Inputs  
DDRB4 = 0  
DDRB5 = 0  
ISEN = 0  
ISEN = 0  
ICEN = 0  
15.7 CURRENT SOURCE FEATURES  
The internal current source connected to the CAP pin supplies about 100 µA of  
current when the ramp discharge device is disabled and the current source is  
active. Therefore this current source can be used in an application if the ISEN  
enable bit is set to power up the current source is enabled by setting the A/D con-  
version method to manual Mode 0 (ATD1 and ATD2 cleared) and the charge cur-  
rent enabled (CHG set).  
15.8 SAMPLE AND HOLD  
When using the internal sample capacitor to capture a voltage for later conver-  
sion, the HOLD and DHOLD bit must be cleared first before changing any channel  
selection. If both the HOLD (or DHOLD) bit and the channel selection are  
changed on the same write cycle, the sample may be corrupted during the switch-  
ing transitions.  
NOTE  
The sample capacitor can be affected by excessive noise created with respect to  
the device’s V pin such that it may appear to leak down or charge up depending  
SS  
on the voltage level stored on the sample capacitor. It is recommended to avoid  
switching large currents through the port pins while a voltage is to remain stored  
on the same capacitor.  
The additional option of adding an offset voltage to the bottom of the sample  
capacitor allows unknown voltages near VSS to be sampled and then shifted up  
past the comparator offset and the device offset caused by a single V return pin.  
SS  
The offset also provides a means to measure the internal V level regardless of  
SS  
the comparator offset in order to determine N  
as described in Section 15.5.  
OFF  
15.9 PORT B INTERACTION WITH ANALOG INPUTS  
The analog subsystem is connected directly to the Port B I/O pins without any  
intervening gates. It is therefore possible to measure the voltages on Port B pins  
set as inputs; or to have the analog voltage measurements corrupted by Port B  
pins set as outputs.  
MOTOROLA  
15-30  
ANALOG SUBSYSTEM  
MC68HC05SB7  
REV 2.1  
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