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68HC705PL4B 参数 Datasheet PDF下载

68HC705PL4B图片预览
型号: 68HC705PL4B
PDF下载: 下载PDF文件 查看货源
内容描述: 工业标准的8位M68HC05 CPU核心 [Industry standard 8-bit M68HC05 CPU core]
分类和应用:
文件页数/大小: 98 页 / 1158 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
April 30, 1998  
GENERAL RELEASE SPECIFICATION  
9.7  
9.8  
16-BIT TIMER OPERATION DURING WAIT MODE  
During WAIT mode the 16-bit timer continues to operate normally and may gener-  
ate an interrupt to trigger the MCU out of the WAIT mode.  
16-BIT TIMER OPERATION DURING STOP MODE  
When the MCU enters the STOP mode the free-running counter stops counting  
(the internal processor clock is stopped). It remains at that particular count value  
until the STOP mode is exited by applying a low signal to the IRQ pin, at which  
time the counter resumes from its stopped value as if nothing had happened. If  
STOP mode is exited via an external reset (logic low applied to the RESET pin)  
the counter is forced to timer interrupt vector.  
If a valid input capture edge occurs at the PA2/TCAP pin during the STOP mode  
the input capture detect circuitry will be armed. This action does not set any ags  
or “wake up” the MCU, but when the MCU does “wake up” there will be an active  
input capture ag (and data) from the rst v alid edge. If the STOP mode is exited  
by an external reset, no input capture ag or data will be present even if a valid  
input capture edge was detected during the STOP mode.  
MC68HC05PL4  
REV 2.0  
16-BIT PROGRAMMABLE TIMER  
9-11  
For More Information On This Product,  
Go to: www.freescale.com