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68HC705PL4B 参数 Datasheet PDF下载

68HC705PL4B图片预览
型号: 68HC705PL4B
PDF下载: 下载PDF文件 查看货源
内容描述: 工业标准的8位M68HC05 CPU核心 [Industry standard 8-bit M68HC05 CPU core]
分类和应用:
文件页数/大小: 98 页 / 1158 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
GENERAL RELEASE SPECIFICATION  
April 30, 1998  
TCMPEN - TIMER OUTPUT COMPARE ENABLE  
The bit con gures por t pin PA3 for Timer16 output compare function (TCMP).  
At power-on-reset, this bit is cleared, PA3 is a standard I/O port pin, TCMP sig-  
nal to PA3 is disabled from Timer16.  
1 = PA3 pin con gured as TCMP for timer output compare  
0 = PA3 pin as standard I/O port pin  
9.6  
TIMER STATUS REGISTER (TSR)  
The timer status register (TSR) shown in Figure 9-12 contains ags f or the follow-  
ing events:  
An active signal on the PA2/TCAP pin transferring the contents of the  
timer registers to the input capture registers.  
A match between the 16-bit counter and the output compare registers,  
transferring the OLVL bit to the TCMP.  
An over o w of the timer registers from $FFFF to $0000.  
Writing to any of the bits in the TSR has no effect. Reset does not change the  
state of any of the ag bits in the TSR.  
BIT 7  
ICF  
BIT 6  
OCF  
BIT 5  
TOF  
BIT 4  
0
BIT 3  
0
BIT 2  
0
BIT 1  
0
BIT 0  
0
TSR  
R
$0013  
W
reset:  
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET  
Figure 9-12. Timer Status Registers (TSR)  
ICF - INPUT CAPTURE FLAG  
The ICF bit is automatically set when an edge of the selected polarity occurs on  
the PA2/TCAP pin. Clear the ICF bit by reading the timer status register with  
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture  
registers. Resets have no effect on ICF.  
OCF - OUTPUT COMPARE FLAG  
The OCF bit is automatically set when the value of the timer registers matches  
the contents of the output compare registers. Clear the OCF bit by reading the  
timer status register with the OCF set, and then accessing the low byte (OCRL,  
$0017) of the output compare registers. Resets have no effect on OCF.  
TOF - TIMER OVERFLOW FLAG  
The TOF bit is automatically set when the 16-bit timer counter rolls over from  
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the  
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.  
Resets have no effect on TOF.  
16-BIT PROGRAMMABLE TIMER  
MC68HC05PL4  
REV 2.0  
9-10  
For More Information On This Product,  
Go to: www.freescale.com