Freescale Semiconductor, Inc.
Parallel Input/Output
Port A
7.3.3 Pulld own Re g iste r A (PDRA)
All port A pins can have software programmable pulldown devices
enabled or disabled globally by SWPDI bit in the MOR. These pulldown
devices are controlled by the write-only pulldown register A (PDRA)
shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns
on the pulldown devices if the port A pin is an input. Reading the PDRA
returns undefined results since it is a write-only register, therefore do not
change the value in PDRA with read/modify/write instructions. On the
MC68HC705JP7 the PDRA contains two pulldown control bits (PDICH
and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH and
PDICL bits, which turns on all the port A and port C pulldown devices.
$0010
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write: PDICH
Reset:
PDICL
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on
the upper four bits (PC4:7). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on
the lower four bits (PC0:3). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICL.
1 = Lower four port C pins pulldown devices turned off
0 = Lower four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
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