Freescale Semiconductor, Inc.
Parallel Input/Output
Port A
7.3.1 Port A Da ta Re g iste r (PORTA)
The port A data register contains a bit for each of the port A pins. When
a port A pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin. The upper two bits of the port A data register will
always read as logical zeros.
$0000
Read:
Bit 7
0
6
0
5
4
3
2
1
Bit 0
PA0
PA5
PA4
PA3
PA2
PA1
Write:
Reset:
Unaffected by Reset
KYBD3 KYBD2 KYBD1 KYBD0
Alternate:
= Unimplemented
Figure 7-1. Port A Data Register (PORTA)
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in the port A data
direction register (DDRA). Reset has no effect on port A data.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
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