Freescale Semiconductor, Inc.
Core Timer
Core Timer Counter Register (CTCR)
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
Real-Time
Interrupt Period
(RTI)
COP Timeout Period
COP = 7 to 8 RTI Periods
(milliseconds)
11
TOF = 1/(f
÷ 2 )
OSC
RTI
(milliseconds)
(microseconds)
Rate
= f
RT1 RT0
OSC
divided
by:
@ f (MHz)
@ f
(MHz)
@ f
(MHz)
OSC
OSC
OSC
4.2 MHz
Min Max
7.80 16.4 32.8 54.6 62.4
2.0 MHz
1.0 MHz
4.2
2.0
1.0
4.2
2.0
1.0
MHz MHz MHz
MHz MHz MHz
Min
Max
131
262
524
Min
Max
262
524
15
0
0
1
1
0
1
0
1
2
115
229
459
229
459
16
2
15.6 32.8 65.5
109
218
437
125
250
499
488 1024 2048
17
2
31.2 65.5
62.4 131
131
262
918 1049
18
2
918 1049 1835 2097
10.4 Core Tim e r Counte r Re g iste r (CTCR)
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure 10-3.
$0009
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on the DELAY bit in the mask option register (MOR)), the
power-on reset circuit is released, clearing the counter again and
allowing the MCU to come out of reset.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Core Timer
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