Freescale Semiconductor, Inc.
Core Timer
Core Timer Status and Control Register (CTSCR)
10.3 Core Tim e r Sta tus a nd Control Re g iste r (CTSCR)
The read/write core timer status and control register (CTSCR) contains
the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and
the rate selects for the real time interrupt as shown in Figure 10-2.
$0008
Read:
Write:
Reset:
Bit 7
6
5
CTOFE
0
4
RTIE
0
3
2
1
RT1
1
Bit 0
RT0
1
CTOF
RTIF
0
CTOFR
0
0
RTIFR
0
0
0
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the core
timer counter roll over from $FF to $00. The CTOF flag bit generates
a timer overflow interrupt request if CTOFE is also set. The CTOF flag
bit is cleared by writing a logic one to the CTOFR bit. Writing to CTOF
has no effect. Reset clears CTOF.
1 = Overflow in core timer has occurred
0 = No overflow of core timer since CTOF last cleared
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. The RTIF enable bit is cleared by writing a
logic one to the RTIFR bit. Writing to RTIF has no effect. Reset clears
RTIF.
1 = Overflow in real-time counter has occurred
0 = No overflow of real-time counter since RTIF last cleared
CTOFE — Core Timer Overflow Interrupt Enable
This read/write bit enables core timer overflow interrupts. Reset
clears CTOFE.
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Core Timer
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