Freescale Semiconductor, Inc.
Pa ra lle l Inp ut/ Outp ut
Table 7-3. Port B Pin Functions — PB5:7
Control Bits
PORTB Access
(Pin or Data
Register)
Result on
Port B
SIOP
Pin
Port B Pins
SWPDI
in
MOR
Port B
SPE
MSTR
PDIBx DDRBx*
Read
Pin
Write
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Pulldown
Pin
0
0
1
X
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
PB5 In
PB5 In
PB5 In
PB5 Out
SDO Out
SDO Out
PB6 In
PB6 In
PB6 In
PB6 Out
SDI In
Pin
0
X
X
X
Pin
PB5
Data
SDO
Data
Pin
1
0
1
0
X
X
X
X
X
X
0
0
1
X
0
1
Pin
X
X
Pin
PB6
Data
SDI
Data
Pin
X
X
SDI In
0
0
1
X
0
1
PB7 In
PB7 In
PB7 In
PB7 Out
SCK In
SCK In
SCK Out
SCK Out
Pin
X
X
Pin
Data
SCK
Data
SCK
Data
PB7
0
1
X
X
X
X
1
* DDRB can always be read or written.
X = Don’t Care
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
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