Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Index Register (X)
3.4 Ind e x Re g iste r (X)
The index register is a general-purpose 8-bit register as shown in Figure
3-3. In the indexed addressing modes, the CPU uses the byte in the
index register to determine the conditional address of the operand.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 3-3. Index Register (X)
The 8-bit index register can also serve as a temporary data storage
location.
3.5 Sta c k Pointe r (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack as shown in Figure 3-4. During a reset or after the
reset stack pointer (RSP) instruction, the stack pointer initializes to
$00FF. The address in the stack pointer decrements as data is pushed
onto the stack and increments as data is pulled from the stack.
Bit
Bit
0
15 14 13 12 11 10
9
0
0
8
0
0
7
1
1
6
1
1
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Figure 3-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Central Processor Unit (CPU)
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