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68HC705JJ7_1 参数 Datasheet PDF下载

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型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Instruc tion Se t  
14.4.3 Jum p / Bra nc h Instruc tions  
Jump instructions allow the CPU to interrupt the normal sequence of the  
program counter. The unconditional jump instruction (JMP) and the  
jump-to-subroutine instruction (JSR) have no register operand. Branch  
instructions allow the CPU to interrupt the normal sequence of the  
program counter when a test condition is met. If the test condition is not  
met, the branch is not performed.  
The BRCLR and BRSET instructions cause a branch based on the state  
of any readable bit in the first 256 memory locations. These 3-byte  
instructions use a combination of direct addressing and relative  
addressing. The direct address of the byte to be tested is in the byte  
following the opcode. The third byte is the signed offset byte. The CPU  
finds the effective branch destination by adding the third byte to the  
program counter if the specified bit tests true. The bit to be tested and its  
condition (set or clear) is part of the opcode. The span of branching is  
from –128 to +127 from the address of the next location after the branch  
instruction. The CPU also transfers the tested bit to the carry/borrow bit  
of the condition code register.  
General Release Specification  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
Instruction Set  
For More Information On This Product,  
Go to: www.freescale.com  
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