欢迎访问ic37.com |
会员登录 免费注册
发布采购

68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
 浏览型号68HC705JJ7_1的Datasheet PDF文件第186页浏览型号68HC705JJ7_1的Datasheet PDF文件第187页浏览型号68HC705JJ7_1的Datasheet PDF文件第188页浏览型号68HC705JJ7_1的Datasheet PDF文件第189页浏览型号68HC705JJ7_1的Datasheet PDF文件第191页浏览型号68HC705JJ7_1的Datasheet PDF文件第192页浏览型号68HC705JJ7_1的Datasheet PDF文件第193页浏览型号68HC705JJ7_1的Datasheet PDF文件第194页  
Freescale Semiconductor, Inc.  
Instruc tion Se t  
14.3.5 Ind e xe d , No Offse t  
Indexed instructions with no offset are 1-byte instructions that can  
access data with variable addresses within the first 256 memory  
locations. The index register contains the low byte of the effective  
address of the operand. The CPU automatically uses $00 as the high  
byte, so these instructions can address locations $0000–$00FF.  
Indexed, no offset instructions are often used to move a pointer through  
a table or to hold the address of a frequently used RAM or I/O location.  
14.3.6 Ind e xe d , 8-Bit Offse t  
Indexed, 8-bit offset instructions are 2-byte instructions that can access  
data with variable addresses within the first 511 memory locations. The  
CPU adds the unsigned byte in the index register to the unsigned byte  
following the opcode. The sum is the effective address of the operand.  
These instructions can access locations $0000–$01FE.  
Indexed 8-bit offset instructions are useful for selecting the kth element  
in an n-element table. The table can begin anywhere within the first 256  
memory locations and could extend as far as location 510 ($01FE). The  
k value is typically in the index register, and the address of the beginning  
of the table is in the byte following the opcode.  
14.3.7 Ind e xe d ,16-Bit Offse t  
Indexed, 16-bit offset instructions are 3-byte instructions that can access  
data with variable addresses at any location in memory. The CPU adds  
the unsigned byte in the index register to the two unsigned bytes  
following the opcode. The sum is the effective address of the operand.  
The first byte after the opcode is the high byte of the 16-bit offset; the  
second byte is the low byte of the offset.  
Indexed, 16-bit offset instructions are useful for selecting the kth element  
in an n-element table anywhere in memory.  
As with direct and extended addressing, the Motorola assembler  
determines the shortest form of indexed addressing.  
General Release Specification  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
Instruction Set  
For More Information On This Product,  
Go to: www.freescale.com  
 复制成功!