Freescale Semiconductor, Inc.
EPROM/ OTPROM
$1FF1
Read:
Bit 7
6
5
4
3
2
1
Bit 0
SWPDI
DELAY OSCRES SWAIT
LVREN
PIRQ
LEVEL COPEN
Write:
Reset:
Erased:
Unaffected by Reset
0
0
0
0
0
0
0
0
Figure 13-2. Mask Option Register (MOR)
SWPDI — Software Pulldown Inhibit
This EPROM bit inhibits software control of the port A and port B
pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
DELAY — Stop Startup Delay
This EPROM bit selects the number of bus cycles that must elapse
before bus activity begins following a restart from the stop mode.
1 = Startup delay is 4064 bus cycles
0 = Startup delay is 16 bus cycles
CAUTION: The 16-cycle delay option will work properly in devices with the internal
low power oscillator or with a steady external clock source. Check
crystal/ceramic resonator specifications carefully before using the 16-
cycle delay option with a crystal or ceramic resonator.
OSCRES — Oscillator Resistor
This EPROM bit configures the on-chip oscillator an internal shunt
resistor.
1 = Oscillator configured with 2 M shunt resistor
0 = Oscillator configured without a shunt resistor
NOTE: The optional oscillator resistor is NOT recommended for devices that
use an external RC oscillator. For such devices, this bit should be left
erased as a zero.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
EPROM/OTPROM
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