Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
Table 6-1: Mode Select Summary
MODE
RESET
IRQ
L or H
PB5
USER MODE
X
H
SELF CHECK/BOOTSTRAP
V
TST
V
= 1.8 x VDD
TST
Single
Chip Mode
H
L
RESET
V
TST
H
L
IRQ
PB5
H
L
V
= 1.8 x V
H = V
L = V
SS
TST
DD
DD
Figure 6-1: Mode Entry Diagram
6.5
EPROM Programming
The 11.5K bytes of USER EPROM is positioned at $1000 through $3DFF with the vector
space from $3FF0 to $3FFF. The erased state of EPROM is read as $FF and EPROM
power is supplied from VPP and VDD pins.
The Programming Control Register (PCR) is provided for the EPROM programming. The
function of EPROM depends on the device operating mode.
In the User Mode, ELAT and PGM bits in the PCR are available for the user read/write and
the remaining test bits become read only bits.
Please contact Motorola for Programming boards availability.
6.5.1
Programming Sequence
The EPROM programming is as follows:
- Set the ELAT bit
- Write the data to the address to be programmed
- Set the PGM bit
- Delay for the appropriate amount of time
- Clear the PGM and the ELAT bit
The last item may be done on a single CPU write. It is important to remember that an
external programming voltage must be applied to the VPP pin while programming, but it
should remain between VDD and VSS during normal operation.
SECTION 6: OPERATING MODES
Page 30
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