Freescale Semiconductor, Inc.
General Description
Functional Pin Descriptions
internal Schmitt trigger as part of its input to improve noise immunity.
Each of the PC0 through PC7 I/O pins may be connected as an OR
function with the IRQ interrupt function. This capability allows keyboard
scan applications where the transitions on the I/O pins will behave the
same as the IRQ pin. The edge or level sensitivity selected by a mask
option for the IRQ pin does not apply to the port C input/output (I/O) pin
interrupt. The I/O pin interrupt is always negative edge-sensitive. See
Section 4. Interrupts for more details on the interrupts.
1.6.8 PA0–PA6
These seven I/O lines comprise port A. The state of any pin is software
programmable, and all port A lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.6.9 PB0–PB3 (SPI Pins), PB4/ PWMA, PB5/ PWMB, PB6/ TCMP, a nd PB7/ TCAP
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
PB0–PB3 are shared with serial peripheral interface (SPI) functions. See
Section 10. Serial Peripheral Interface (SPI) for more details
concerning the operation of the SPI and configuration of these pins.
PB6 and PB7 are also shared with timer functions. The TCAP pin
controls the input capture feature for the on-chip 16-bit timer. The TCMP
pin provides an output for the output compare feature of the on-chip 16-
bit timer. See Section 9. 16-Bit Timer for more details on the operation
of the timer subsystem.
PB4 and PB5 are shared with the pulse width modulator output pins
(PWMA and PWMB). See Section 11. Pulse Width Modulators
(PWMs) for more details on the operation of the PWMs.
MC68HC05V12 — Rev. 1.0
General Release Specification
General Description
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
