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68HC05V12 参数 Datasheet PDF下载

68HC05V12图片预览
型号: 68HC05V12
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 240 页 / 5838 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Ge ne ra l De sc rip tion  
1.6.5.3 Exte rna l Clo c k  
An external clock from another CMOS-compatible device can be  
connected to the OSC1 input. The OSC2 pin should be left unconnected,  
as shown in Figure 1-3(b).  
MCU  
MCU  
OSC1  
OSC2  
OSC1  
OSC2  
10 M*  
UNCONNECTED  
20 pF *  
20 pF *  
4 MHz*  
EXTERNAL CLOCK  
(a) Crystal or Ceramic  
Resonator Connens  
(b)External Clock  
Source Connection  
*Values shown are typical. For further information, consult the crystal oscillator vendor.  
Figure 1-3. Oscillator Connections  
1.6.6 RESET  
This pin can be used as an input to reset the MCU to a known startup  
state by pulling it to the low state. The RESET pin contains an internal  
Schmitt trigger to improve its noise immunity as an input. The RESET pin  
has an internal pulldown device that pulls the RESET pin low when there  
is an internal computer operating properly (COP) watchdog reset,  
power-oreset (POR), illegal address reset, a disabled STOP  
instruction reset or an internal low-voltage reset. Refer to  
Section 5. Resets.  
1.6.7 IRQ (Ma ska b le Intrup t Re q ue st)  
This input pin drives the asynchronous IRQ interrupt function of the  
CPU. The IRQ interrupt function has a programmable mask option to  
select either negative edge-sensitive triggering or both negative edge-  
sensitive and low level-sensitive triggering. The IRQ input requires an  
external resistor to V for wire-OR operation, if desired. If the IRQ pin  
DD  
is not used, it must be tied to the V supply. The IRQ pin contains an  
DD  
General Release Specification  
MC68HC05V12 Rev. 1.0  
General Description  
For More Information On This Product,  
Go to: www.freescale.com