Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt rst. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in
Figure 4-1
•
•
Sets the I bit in the condition code register to prevent further interrupts
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt is shown in the o w chart in Figure 4-2
$0020
$0021
(Bottom of RAM)
$00BE
$00BF
$00C0
$00C1
$00C2
(Bottom of Stack)
Unstacking
Order
n
n+1
n+2
n+3
n+4
Condition Code Register
Accumulator
5
4
3
2
1
1
2
3
4
5
Index Register
Program Counter (High Byte)
Program Counter (Low Byte)
Stacking
Order
$00FD
$00FE
$00FF
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
INTERRUPTS
MC68HC05PL4
REV 2.0
4-2
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