Freescale Semiconductor, Inc.
April 30, 1998
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
The CPU can be interrupted by ve different sources – one software and four
hardware:
•
•
•
•
•
Non-maskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
16-Bit Timer
8-Bit Timer
Keyboard Interrupt
4.1
INTERRUPT VECTORS
Table 4-1 summarizes the reset and interrupt sources and vector assignments
Table 4-1. Vector Address for Interrupts and Reset
Local
Mask
Global
Mask
Priority
(1=Highest)
Vector
Address
Function
Source
Power-On Logic
RESET Pin
None
None
Reset
None
1
$1FFE-$1FFF
1
COP Watchdog
COPON
Same Priority
As Instruction
SWI
User Code
None
None
I Bit
$1FFC-$1FFD
$1FFA-$1FFB
External IRQ
IRQ Pin
ICF Bit
TCF Bit
OCF Bit
T8IF Bit
KIF3 Bit
KIF2 Bit
KIF1 Bit
KIF0 Bit
—
IRQEN
ICIE
TCIE
OCIE
T8IE
KIE3
KIE2
KIE1
KIE0
—
2
3
4
16-Bit Timer
8-Bit Timer
I Bit
I Bit
$1FF8-$1FF9
$1FF6-$1FF7
Keyboard
I Bit
5
$1FF4-$1FF5
Reserved
Reserved
—
—
—
—
$1FF2-$1FF3
$1FF0-$1FF1
—
—
NOTES:
1. COPON enables/disables the COP watchdog timer.
MC68HC05PL4
REV 2.0
INTERRUPTS
4-1
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