Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
1.2
MCU BLOCK DIAGRAM
4
PB0/KBI0
PB1/KBI1
PB2/KBI2
PB3/KBI3
USER ROM - 4k BYTES
USER RAM - 256 BYTES
KEYBOARD
INTERRUPT
T
D
OP R
4
PB4- PB7
7
0
0
ACCUMULATOR
M68HC05
CPU
PA6
PA5
7
0
PA4
T
INDEX REGISTER
PA3/TCMP
PA2/TCAP
PA1/DTMF
12
0
5
1
0
D
OP R
0
0
0
1
DTMF
MODULE
STACK POINTER
†
15
4
0
PA0
PROGRAM COUNTER
7
1
0
LED
DRIVE
1
1 H
I
N Z C
LED/IRQ
RESET
CONDITION CODE REGISTER
VERY LOW
OSC1
††
OSC
N OPTIONAL)
16-BIT
PROGRAMMABLE TIMER
FREQUENCY OSC
(÷
OSC2
(RC: 500kHz or 20kHz)
8-BIT RELOADABLE
EVENT TIMER
WATCHDOG
SYSTEM
VDD
VSS
POWER
8
†
PC0 - PC7
Available on MC68HC05PL4 only.
Available on MC68HC05PL4B only.
††
Figure 1-1. MC68HC05PL4 Block Diagram
NOTE
A line over a signal name indicates an active low signal. Any reference to voltage,
current, or frequency speci ed in the following sections will refer to the nominal
values. The exact values and their tolerance or limits are speci ed in Electrical
Speci cations section.
GENERAL DESCRIPTION
MC68HC05PL4
REV 2.0
1-2
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