Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05CT4
Se c tion 9. Sync hronous Se ria l Inte rfa c e (SSI)
9.1 Conte nts
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
9.3
9.3.1
9.3.2
Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Serial Data In/Out (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.4
SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SSI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.4.1
9.4.2
9.4.3
9.5
9.6
9.7
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
SSI Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.2 Introd uc tion
The synchronous serial interface (SSI) is a 2-wire master/slave system
including serial clock (SCK) and serial data input/output (SDIO). Data is
transferred eight bits at a time. A software programmable option
determines whether the SSI transfers data most significant bit (MSB) or
least significant bit (LSB) first and an interrupt may be generated at the
completion of each transfer. When operating as a master device, the
serial clock speed is selectable from a choice of four rates.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Synchronous Serial Interface (SSI)
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