General
7.4.1 Device clock specifications
Table 12. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYSCLK
Device (system and core) clock frequency
• using relaxation oscillator
0.001
0
60
60
60
MHz
MHz
• using external clock source
fIPBUS
IP bus clock
—
7.4.2 General Switching Timing
Table 13. Switching Timing
Symbol Description
GPIO pin interrupt pulse width1
Synchronous path
Min
Max
Unit
Notes
1.5
IP Bus
Clock
Cycles
2
Port rise and fall time (high drive strength), Slew disabled 2.7
≤ VDD ≤ 3.6V.
5.5
1.5
8.2
3.2
15.1
6.8
ns
ns
ns
ns
3
3
4
4
Port rise and fall time (high drive strength), Slew enabled 2.7
≤ VDD ≤ 3.6V.
Port rise and fall time (low drive strength). Slew disabled . 2.7
≤ VDD ≤ 3.6V
17.8
9.2
Port rise and fall time (low drive strength). Slew enabled . 2.7
≤ VDD ≤ 3.6V
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. The greater synchronous and asynchronous timing must be met.
3. 75 pF load
4. 15 pF load
7.5 Thermal specifications
7.5.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature (extended industrial)
TA
105
°C
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
32
Freescale Semiconductor, Inc.
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