PWMs and timers
8.6.2 Quad Timer Timing
Parameters listed are guaranteed by design.
Table 31. Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min1
2T + 6
1T + 3
25
Max
—
Unit
ns
See Figure
Figure 14
Figure 14
Figure 14
Figure 14
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
12.5
—
ns
1. T = clock cycle. For 80 MHz operation, T = 12.5 ns.
Timer Inputs
P
P
INHL
INHL
P
IN
Timer Outputs
P
P
OUTHL
OUTHL
P
OUT
Figure 14. Timer Timing
8.7 Communication interfaces
8.7.1 Queued Serial Peripheral Interface (SPI) Timing
Parameters listed are guaranteed by design.
Table 32. SPI Timing
Characteristic
Cycle time
Master
Symbol
Min
Max
Unit
See Figure
Figure 15
Figure 16
Figure 17
Figure 18
tC
45
45
—
—
ns
ns
Slave
Table continues on the next page...
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
52
Freescale Semiconductor, Inc.
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