PWMs and timers
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
8.6 PWMs and timers
8.6.1 Enhanced NanoEdge PWM Characteristics
Table 30. NanoEdge PWM Timing Parameters
Characteristic
Symbol
Min
80
Typ
80
Max
100
396
Unit
MHz
ps
PWM clock frequency
NanoEdge Placement (NEP) Step Size1, 2
Delay for fault input activating to PWM output deactivated
Power-up Time3
pwmp
—
384
1
390
—
ns
tpu
25
µs
1. Reference IPbus clock of 80 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
51
Preliminary
General Business Information
FREESCALE [ Freescale ]
