System modules
7. Offset over the conversion range of 0025 to 4080
8. Measured converting a 1 kHz input Full Scale sine wave
9. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
8.5.1.1 Equivalent Circuit for ADC Inputs
The following figure illustrates the ADC input circuit during sample and hold. S1 and S2
are always opened/closed at non-overlapping phases and operate at the ADC clock
frequency. The following equation gives equivalent input impedance when the input is
selected.
1
100ohm + 125ohm
+
-12
(ADC ClockRate) x 1.4x10
C1: Single Ended Mode
2XC1: Differential Mode
Channel Mux
equivalent resistance
100Ohms
S1
125 ESD
Resistor
Analog Input
C1
C1
S1
S1
S/H
3
1
2
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1: Single Ended Mode
2XC1: Differential Mode
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling;
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing; 2.04pF
3. 8 pF noise damping capacitor
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally
disconnected from the input and is only connected to it at sampling time; 1.4pF for
x1 gain; 2.8pf for x2 gain, and 5.6pf for x4 gain
5. S1 and S2 switch phases are non-overlapping and operate at the ADC clock
frequency
S1
S2
Figure 9. Equivalent Circuit for A/D Loading
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
43
Preliminary
General Business Information
FREESCALE [ Freescale ]
