System modules
Table 25. 12-bit ADC Electrical Specifications (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
ADC RUN Current (per ADC block)
• at 600 kHz ADC Clock, LP mode
• ≤ 8.33 MHz ADC Clock, 00 mode
• ≤ 12.5 MHz ADC Clock, 01 mode
• ≤ 16.67 MHz ADC Clock, 10 mode
• ≤ 20 MHz ADC Clock, 11 mode
IADRUN
mA
1
5
9
15
19
ADC Powerdown Current (adc_pdn enabled)
VREFH Current
IADPWRDWN
IVREFH
0.02
µA
µA
0.001
Accuracy (DC or Absolute)
Integral non-Linearity5
Differential non-Linearity5
INL
+/- 3
+/- 5
+/- 1
LSB6
LSB6
DNL
+/- 0.6
Monotonicity
Offset7
VOFFSET
mV
• ≤15 MHz ADC Clock Internal/External
Reference
• >15 MHz ADC Clock Internal/External
Reference
+/- 4.03
+/- 7.25
+/- 8.86
+/- 13.70
Gain Error
EGAIN
0.801 to
0.809
0.798 to
0.814
mV
AC Specifications8
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to Noise plus Distortion
Effective Number of Bits
ADC Inputs
SNR
THD
59
64
65
59
9.5
dB
dB
dB
dB
bits
SFDR
SINAD
ENOB
Input Leakage Current
Input Injection Current 9
Input Capacitance
IIN
IINJ
0
+/-2
+/-3
µA
mA
pF
CADI
Sampling Capacitor
• 1x mode
1.4
2.8
5.6
• 2x mode
• 4x mode
1. If the ADC’s reference is from VDDA: When VDDA is below 3.0 V, the ADC functions but ADC specifications are not
guaranteed.
2. When the input is at the Vrefl level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset
and gain error. When the input is at the Vrefh level the output will be all ones (hex FFF), minus any error contribution due to
offset and gain error.
3. ADC clock duty cycle min/max is 45/55%
4. When Vrefh is supplied externally
5. INL measured from VIN = VREFL to VIN = V
.
6. LSB = Least Significant Bit = 0.806 mV atR3EF.H3 V VDDA, x1 Gain Setting
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
42
Freescale Semiconductor, Inc.
Preliminary
General Business Information
FREESCALE [ Freescale ]
