General
Table 7. DC Electrical Characteristics at Recommended Operating Conditions (continued)
Characteristic
Symbol
Notes1
Min
Typ
Max
Unit
µA
V
Test
Conditions
Oscillator Input Current
Low
IILOSC
Pin Group 3
Pin Group 5
—
0
+/- 2
VIN = 0V
DAC Output Voltage
Range
VDAC
Typically
—
Typically
VDDA -
RLD = 3 kΩ ||
CLD = 400 pf
VSSA
+
40mV
40mV
Output Current1
IOZ
Pin Groups
1, 2
—
0
+/- 1
µA
V
—
—
High Impedance State
Schmitt Trigger Input
Hysteresis
VHYS
Pin Groups 0.06 x VDD
1, 2
—
—
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET, GPIOA7
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
7.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 8. Reset, Stop, Wait, and Interrupt Timing
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
tRDA
tIF
161
TBD
361.3
—
162
ns
ns
ns
—
—
—
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first instruction
(exiting Stop)
570.9
1. If Reset pin filter is enabled, minimum pulse assertion must be greater than 21 ns
2. This value is true if the user sets to 1 the RST_FLT bit in the SIM_CTRL register.
NOTE
In the formulae, T = system clock cycle and Tosc = oscillator
clock cycle. For an operating frequency of 80 MHz,
T = 12.5 ns. At 4 MHz (used coming out of reset and stop
modes), T = 250 ns.
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
28
Freescale Semiconductor, Inc.
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