Peripheral highlights
• Dual slave addresses
• Programmable glitch input filter
1.6.10 Flex Controller Area Network (FlexCAN) Module
• Clock source from PLL or XOSC/CLKIN
• Implementation of the CAN protocol Version 2.0 A/B
• Standard and extended data frames
• 0-to-8 bytes data length
• Programmable bit rate up to 1 Mbps
• Support for remote frames
• Sixteen Message Buffers, each configurable as receive or transmit, all supporting
standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Internal timer for time-stamping of received and transmitted messages
• Listen-only mode capability
• Programmable loopback mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Global network time, synchronized by a specific message
• Low power modes, with programmable wakeup on bus activity
1.6.11 Computer Operating Properly (COP) Watchdog
• Programmable timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator/external clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
1.6.12 Power Supervisor
• Power-on reset (POR) to reset CPU, peripherals, and JTAG/EOnCE controllers
(VDD > 2.1 V)
MC56F847xx Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
11
Preliminary
General Business Information
FREESCALE [ Freescale ]
