欢迎访问ic37.com |
会员登录 免费注册
发布采购

56F84441VLF 参数 Datasheet PDF下载

56F84441VLF图片预览
型号: 56F84441VLF
PDF下载: 下载PDF文件 查看货源
内容描述: MC56F844xx进展 [MC56F844xx Advance]
分类和应用:
文件页数/大小: 67 页 / 988 K
品牌: FREESCALE [ Freescale ]
 浏览型号56F84441VLF的Datasheet PDF文件第52页浏览型号56F84441VLF的Datasheet PDF文件第53页浏览型号56F84441VLF的Datasheet PDF文件第54页浏览型号56F84441VLF的Datasheet PDF文件第55页浏览型号56F84441VLF的Datasheet PDF文件第57页浏览型号56F84441VLF的Datasheet PDF文件第58页浏览型号56F84441VLF的Datasheet PDF文件第59页浏览型号56F84441VLF的Datasheet PDF文件第60页  
PWMs and timers  
8.7.2 Queued Serial Communication Interface (SCI) Timing  
Parameters listed are guaranteed by design.  
Table 33. SCI Timing  
Characteristic  
Baud rate1  
Symbol  
BR  
Min  
Max  
Unit  
Mbps  
ns  
See Figure  
(fMAX/16)  
1.04/BR  
1.04/BR  
RXD pulse width  
TXD pulse width  
RXDPW  
TXDPW  
0.965/BR  
0.965/BR  
Figure 19  
Figure 20  
ns  
LIN Slave Mode  
Deviation of slave node clock from nominal FTOL_UNSYNCH  
clock rate before synchronization  
-14  
14  
2
%
%
Deviation of slave node clock relative to  
the master node clock after  
synchronization  
FTOL_SYNCH  
-2  
Minimum break character length  
TBREAK  
13  
11  
Master  
node bit  
periods  
Slave node  
bit periods  
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected system clock (max. 120 MHz depending  
on part number) or 2x system clock (max. 200 MHz) for the devices.  
RXD  
SCI receive  
data pin  
RXD  
PW  
(Input)  
Figure 19. RXD Pulse Width  
TXD  
SCI transmit  
data pin  
TXD  
PW  
(output)  
Figure 20. TXD Pulse Width  
8.7.3 Freescale’s Scalable Controller Area Network (FlexCAN)  
Table 34. FlexCAN Timing Parameters  
Characteristic  
Baud Rate  
Symbol  
BRCAN  
Min  
5
Max  
1
Unit  
Mbps  
µs  
CAN Wakeup dominant pulse filtered  
CAN Wakeup dominant pulse pass  
TWAKEUP  
TWAKEUP  
2
µs  
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.  
56  
Freescale Semiconductor, Inc.  
Preliminary  
General Business Information  
 复制成功!