PWMs and timers
Table 31. Timer Timing
Characteristic
Symbol
PIN
Min1
2T + 6
1T + 3
33
Max
—
Unit
ns
See Figure
Figure 14
Figure 14
Figure 14
Figure 14
Timer input period
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
16.7
—
ns
1. T = clock cycle. For 60 MHz operation, T = 16.7 ns.
Timer Inputs
P
P
INHL
INHL
P
IN
Timer Outputs
P
P
OUTHL
OUTHL
P
OUT
Figure 14. Timer Timing
8.7 Communication interfaces
8.7.1 Queued Serial Peripheral Interface (SPI) Timing
Parameters listed are guaranteed by design.
Table 32. SPI Timing
Characteristic
Cycle time
Master
Symbol
Min
Max
Unit
See Figure
Figure 15
Figure 16
Figure 17
Figure 18
Figure 18
tC
55
55
—
—
ns
ns
Slave
Enable lead time
Master
tELD
—
—
—
ns
ns
Slave
17.5
Enable lag time
Master
tELG
Figure 18
—
—
—
ns
ns
Slave
17.5
Table continues on the next page...
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
52
Freescale Semiconductor, Inc.
Preliminary
General Business Information