System modules
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
8. System Clock = 4 MHz, ADC Clock = 2 MHz, AVG = Max, Long Sampling = Max
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
8.5.3 12-bit Digital-to-Analog Converter (DAC) Parameters
Table 28. DAC Parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
DC Specifications
Resolution
Settling time1
12
—
12
1
12
bits
µs
At output load
RLD = 3 kΩ
CLD = 400 pf
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is valid
tDAPU
—
—
11
µs
Accuracy
Table continues on the next page...
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
47
Preliminary
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