System modules
8.5.2 16-bit SAR ADC electrical specifications
8.5.2.1 16-bit ADC operating conditions
Table 26. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
2.7
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
Delta to VDD (VDD-VDDA
)
-100
-100
VDDA
0
+100
+100
VDDA
mV
mV
V
2
2
3
Delta to VSS (VSS-VSSA
Absolute
)
0
ADC reference
voltage high
VDDA
VREFL
ADC reference
voltage low
Absolute
VSSA
VSSA
VSSA
V
4
VADIN
CADIN
Input voltage
VSSA
—
—
8
VDDA
10
V
Input capacitance
• 16 bit modes
pF
• 8/10/12 bit modes
—
4
5
RADIN
RAS
Input resistance
—
2
5
kΩ
kΩ
Analog source
resistance
12 bit modes
fADCK < 4MHz
5
—
—
5
fADCK
fADCK
Crate
ADC conversion ≤ 12 bit modes
clock frequency
6
6
7
1.0
2.0
—
—
—
18.0
12.0
MHz
MHz
Ksps
ADC conversion 16 bit modes
clock frequency
ADC conversion ≤ 12 bit modes
rate
No ADC hardware averaging
20.000
818.330
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16 bit modes
7
rate
No ADC hardware averaging
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. VREFH is internally tied to VDDA
4. VREFL is internally tied to VSSA
5. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
.
.
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
6. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
44
Freescale Semiconductor, Inc.
Preliminary
General Business Information
FREESCALE [ Freescale ]
