System modules
8.3.1 External Clock Operation Timing
Parameters listed are guaranteed by design.
Table 18. External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
Typ
Max
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock pulse width2
External clock input rise time3
—
—
50
tPW
8
—
trise
—
—
—
—
1
1
ns
External clock input fall time4
tfall
—
ns
Input high voltage overdrive by an external clock
Input low voltage overdrive by an external clock
Vih
0.85VDD
—
—
V
Vil
0.3VDD
V
1. See Figure 7 for detail on using the recommended connection of an external clock driver.
2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.
V
IH
External
Clock
90%
50%
10%
90%
50%
10%
t
V
IL
t
fall
rise
t
t
PW
PW
Note: The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 7. External Clock Timing
8.3.2 Phase Locked Loop Timing
Table 19. Phase Locked Loop Timing
Characteristic
PLL input reference frequency1
PLL output frequency2
Symbol
fref
Min
8
Typ
8
Max
Unit
MHz
MHz
µs
16
400
73.2
60
fop
240
35.5
40
—
PLL lock time3
tplls
Allowed Duty Cycle of input reference
tdc
50
%
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 60 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.
36
Freescale Semiconductor, Inc.
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