PWMs and timers
SS
(Input)
SS is held high on master
t
C=33.3
t
R
t
F
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
R
t
CL
SCLK (CPOL = 1)
(Output)
t
t
DH
CH
t
DS
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t (ref)
DI
t
DI
DV
MOSI
(Output)
Master MSB out
Bits 14–1
Master LSB out
t
t
R
F
Figure 15. SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
t
C
t
F
t
R
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
CL
SCLK (CPOL = 1)
(Output)
t
CH
t
DS
t
R
t
DH
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t
(ref)
DI
t
DV
t (ref)
DV
DI
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t
t
R
F
Figure 16. SPI Master Timing (CPHA = 1)
MC56F8458x Advance Information Data Sheet, Rev. 2, 06/2012.
54
Freescale Semiconductor, Inc.
Preliminary
General Business Information
FREESCALE [ Freescale ]
