6.7 Power Down Modes Overview
The 56F8367/56F8167 operate in one of three power-down modes as shown in Table 6-3.
Table 6-4 Clock Operation in Power Down Modes
Mode
Run
Core Clocks
Active
Peripheral Clocks
Description
Device is fully functional
Active
Active
Peripherals are active and can produce interrupts if they
have not been masked off.
Wait
Core and memory
clocks disabled
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system
frequency which can be controlled through the OCCS.
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable
Disable
STOP_DIS
D
Q
D-FLOP
Clock
C
R
Select
Note: Wait disable circuit is similar
Reset
Figure 6-17 Stop Disable Circuit
56F8367 Technical Data, Rev. 9
128
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
