Clock Generation Overview
Base + $E
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
ISAL[21:6]
Write
RESET
1
1
Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.5.11 Peripheral Clock Enable Register 2 (SIM_PCE2)
The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a
power-saving feaure. The clocks can be individually controller for each peripheral on the chip.
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CAN
2
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
6.5.11.1 Reserved—Bits 15–1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.11.2 CAN2 Enable—Bit 0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused sub-functions. Refer to Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300
Peripheral User Manual for further details.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
127
FREESCALE [ Freescale ]
