Analog-to-Digital Converter (ADC) Parameters
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-20 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-21 TRST Timing Diagram
10.16 Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters
Characteristic
Symbol
VADIN
RES
Min
VREFL
12
Typ
—
Max
VREFH
12
Unit
V
Input voltages
Resolution
—
Bits
Integral Non-Linearity1
Differential Non-Linearity
LSB2
LSB2
INL
—
+/- 2.4
+/- 0.7
+/- 3.2
< +1
DNL
—
Monotonicity
GUARANTEED
—
ADC internal clock
fADIC
RAD
0.5
VREFL
5
5
MHz
V
Conversion range
—
6
VREFH
16
tAIC cycles3
ADC channel power-up time
tADPU
56F8366 Technical Data, Rev. 6
Freescale Semiconductor
Preliminary
165
FREESCALE [ Freescale ]
