CAN_RX
CAN receive
data pin
T WAKEUP
(Input)
Figure 10-18 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
10-19
TCK frequency of operation
using EOnCE1
fOP
DC
SYS_CLK/8
MHz
TCK frequency of operation not
using EOnCE1
fOP
DC
SYS_CLK/4
MHz
10-19
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
tPW
tDS
50
5
—
—
—
30
30
—
ns
ns
ns
ns
ns
ns
10-19
10-20
10-20
10-20
10-20
10-21
tDH
5
tDV
—
—
tTS
2T2
tTRST
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-19 Test Clock Input Timing Diagram
56F8366 Technical Data, Rev. 6
164
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
