Register Descriptions
5.6.7.1
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.3
Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.5
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
89
FREESCALE [ Freescale ]
