5.6.6.6
SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.7
SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—
Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.8
SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
15
14
13
12
11
10
9
8
7
6
5
0
4
0
3
2
1
0
TMRC0
IPL
TMRD3
IPL
TMRD2
IPL
TMRD1
IPL
TMRD0
IPL
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-9 Interrupt Priority Register 6 (IPR6)
56F8345 Technical Data, Rev. 17
88
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
