Analog-to-Digital Converter (ADC) Parameters
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-18 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-19 Test Access Port Timing Diagram
10.15 Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters
Characteristic
Symbol
VADIN
RES
Min
VREFL
12
Typ
—
Max
VREFH
12
Unit
V
Input voltages
Resolution
—
Bits
Integral Non-Linearity1
Differential Non-Linearity
LSB2
LSB2
INL
—
+/- 2.4
+/- 0.7
+/- 3.2
< +1
DNL
—
Monotonicity
GUARANTEED
—
ADC internal clock
fADIC
RAD
0.5
5
MHz
V
Conversion range
VREFL
—
VREFH
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
Preliminary
121
FREESCALE [ Freescale ]
