Reset, Stop, Wait, Mode Select, and Interrupt Timing
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
Typical Response
- 30
- 50
- 10
+ 10
+ 30
+ 90
+ 150
+ 50
+ 70
+ 110 + 130
Temperature
Figure 10-4 Frequency versus Temperature
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
See
Figure
Characteristic
Symbol
Unit
Minimum RESET Assertion Duration
Edge-sensitive Interrupt Request Width
tRA
tIRW
16T
1.5T
18T
14T
1.5T
—
—
—
—
—
ns
ns
ns
10-5
10-6
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
10-7
tIG - FAST
tIW
IRQA Width Assertion to Recover from Stop State3
ns
10-8
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
Preliminary
113
FREESCALE [ Freescale ]
