External Clock Operation Timing
10.5 External Clock Operation Timing
1
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
0
Typ
—
Max
120
80
Unit
MHz
MHz
ns
Frequency of operation (external clock driver)2—56F8322
Frequency of operation (external clock driver)2—56F8122
Clock Pulse Width3
fosc
0
—
tPW
3.0
—
—
—
—
External clock input rise time4
trise
—
15
ns
External clock input fall time5
tfall
—
15
ns
1. Parameters listed are guaranteed by design.
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
Min
4
Typ
8
Max
8.4
Unit
MHz
MHz
External reference crystal frequency for the PLL1
PLL output frequency2 (fOUT)—56F8322
fosc
fop
160
—
260
PLL output frequency2 (fOUT)—56F8122
fop
160
—
—
1
160
10
MHz
ms
PLL stabilization time3 -40° to +125°C
tplls
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
/2), please refer to the OCCS chapter in the
OUT
56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
Preliminary
111
FREESCALE [ Freescale ]
