Table 10-6 Power-On Reset Low Voltage Parameters
Characteristic
POR Trip Point Rising1
Symbol
PORR
PORF
Min
—
Typ
—
Max
—
Units
V
POR Trip Point Falling
1.75
—
1.8
1.9
—
V
LVI, 2.5V Supply, trip point2
VEI2.5
VEI3.3
2.14
2.7
V
LVI, 3.3V supply, trip point3
Bias Current
—
—
V
I bias
—
110
130
μA
1. Both V
and V
thresholds must be met for POR to be released on power-up.
EI3.3
EI2.5
2. When V
3. When V
drops below V
drops below V
, an interrupt is generated.
, an interrupt is generated.
DD_CORE
DD_CORE
EI2.5
EI3.3
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
1
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
IDD_IO
• 60MHz Device Clock
• All peripheral clocks are enabled
RUN1_MAC
115mA
25mA
2.5mA
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
Wait3
Stop1
60mA
35μA
0μA
2.5mA
• All peripheral clocks are enabled
• ADC powered off
• 4MHz Device Clock
• All peripheral clocks are off
• Relaxation oscillator is on
• ADC powered off
5.7mA
360μA
• PLL powered off
• Relaxation oscillator is off
• All peripheral clocks are off
• ADC powered off
Stop2
5mA
0μA
145μA
• PLL powered off
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
2. Includes Processor Core current supplied by internal voltage regulator
56F8322 Techncial Data, Rev. 16
106
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
