Operating Modes
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
•
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F0E0)
Register
Acronym
Base Address +
Register Name
Section Location
IPR0
$0
$1
Interrupt Priority Register 0
5.6.1
5.6.2
IPR1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High 0 Register
Fast Interrupt Match 1 Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IPR2
$2
5.6.3
IPR3
$3
5.6.4
IPR4
$4
5.6.5
IPR5
$5
5.6.6
IPR6
$6
5.6.7
VBA
$7
5.6.8
FIM0
$8
5.6.9
FIVAL0
FIVAH0
FIM1
$9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
$A
$B
$C
$D
$E
$F
$10
$11
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
Reserved
ICTRL
$16
Interrupt Control Register
5.6.19
Reserved
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
71
FREESCALE [ Freescale ]
