3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts
its Fast Interrupt handling.
5.4 Block Diagram
any0
Priority
Level
Level 0
64 -> 6
Priority
Encoder
6
2 -> 4
Decode
INT1
INT
VAB
IPIC
CONTROL
any3
IACK
SR[9:8]
Level 3
Priority
Level
64 -> 6
Priority
PIC_EN
6
Encoder
2 -> 4
Decode
INT64
Figure 5-1 Interrupt Controller Block Diagram
56F8037/56F8027 Data Sheet, Rev. 6
70
FreescaleSemiconductor
FREESCALE [ Freescale ]
