Peripheral Memory-Mapped Registers
Table 4-7 EOnCE Memory Map (Continued)
Address
X:$FF FF92
Register Acronym
Register Name
Breakpoint Unit Address Register 2
OBAR2 (32 bits)
X:$FF FF91
Breakpoint Unit Mask Register 2
Breakpoint Unit Mask Register 2
Reserved
X:$FF FF90
OBMSK (32 bits)
OBCNTR
X:$FF FF8F
X:$FF FF8E
EOnCE Breakpoint Unit Counter
Reserved
X:$FF FF8D
X:$FF FF8C
Reserved
X:$FF FF8B
Reserved
X:$FF FF8A
OESCR
External Signal Control Register
Reserved
X:$FF FF89 - X:$FF FF00
4.6 Peripheral Memory-Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read or written using word accesses only.
Table 4-8 summarizes base addresses for the set of peripherals on the 56F8037/56F8027 device.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-8 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
Timer A
Timer B
ADC
TMRA
TMRB
ADC
X:$00 F000
X:$00 F040
X:$00 F080
X:$00 F0C0
X:$00 F0E0
X:$00 F100
X:$00 F120
X:$00 F130
X:$00 F140
X:$00 F150
X:$00 F160
X:$00 F170
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F1B0
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
PWM
ITCN
SIM
PWM
ITCN
SIM
COP
COP
CLK, PLL, OSC
Power Supervisor
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
PIT 0
OCCS
PS
GPIOA
GPIOB
GPIOC
GPIOD
PIT0
PIT 1
PIT1
PIT 2
PIT2
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
51
FREESCALE [ Freescale ]
