Program
Data
EOnCE
Reserved
Reserved
RAM
Flash
Peripherals
Reserved
RAM
Dual Port RAM
Reserved
Figure 4-2 Dual Port RAM for 56F8027
4.5 EOnCE Memory Map
Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-7 EOnCE Memory Map
Address
X:$FF FFFF
Register Acronym
Register Name
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE
OTX / ORX (32 bits)
Transmit Register
Receive Register
X:$FF FFFD
X:$FF FFFC
X:$FF FFFB - X:$FF FFA1
X:$FF FFA0
X:$FF FF9F
X:$FF FF9E
X:$FF FF9D
X:$FF FF9C
X:$FF FF9B
X:$FF FF9A
X:$FF FF99
X:$FF FF98
X:$FF FF97
X:$FF FF96
X:$FF FF95
X:$FF FF94
X:$FF FF93
OTXRXSR
OCLSR
Transmit and Receive Status and Control Register
Core Lock / Unlock Status Register
Reserved
OCR
Control Register
Instruction Step Counter
OSCNTR (24 bits)
OSR
Instruction Step Counter
Status Register
OBASE
Peripheral Base Address Register
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
OTBCR
OTBPR
OTB (21 - 24 bits/stage) Trace Buffer Register Stages
Breakpoint Unit Control Register
OBCR (24 bits)
Breakpoint Unit Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
OBAR1 (24 bits)
56F8037/56F8027 Data Sheet, Rev. 6
50
FreescaleSemiconductor
FREESCALE [ Freescale ]
